Agilent N4903B, Keysight N4903B, HP N4903B
J-BERT high-performance serial BERT, 7 Gb/s and 12.5 Gb/s
Telecommunication and Wireless >> Bit Error Ratio Testers (BERT) >> J-BERT high-performance serial BERT, 7 Gb/s and 12.5 Gb/s
Model: N4903B
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Download Product Datasheet
Available Option Configurations
Config-07
- C13 - Pattern Generator and Error Detector 150 Mb/s to 12.5 Gb/s . Includes built-in clock data recovery
- J12 - Jitter tolerance compliance suite
- A02 - Symbol Error Ratio and Frame Error Ratio (SER/FER) Analysis
- J10 - RJ, sRJ, PJ1, PJ2, SJ, BUJ injection
- J11 - Spread Spectrum Clocking (SSC)
- 002 - Pattern and Pseudo Random Pattern Sequence (PRBS) on Auxillary Data Output License
- J20 - Interference Channel, Intersymbol Interference and Sinusoidal Interference
MSRP: $318,147 | Available for Rental GET QUOTE
Config-07
Product Overview
The Agilent / Keysight N4903B J-BERT is a high-performance serial BERT with complete jitter tolerance and is ideal for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s, 12.5Gb/s or 14.2 Gb/s. The pattern generator has significantly low jitter and extremely fast transition times producing clean signals that provide accurate characterization and faster test execution.
With the Agilent / Keysight N4903B J-BERT, test set up is made simple because the N4903B is designed to match serial bus standards optimally with its differential I/Os, variable voltage levels on most outputs, built-in jitter and ISI, pattern sequencer, reference clock outputs, tunable CDR, pattern capture and bit recovery mode to analyze clock-less and non-deterministic patterns. SER/FER analysis allows jitter tolerance testing of devices using retimed loopback. A second data output with independent pattern memory and PRBS can be used as aggressor channel for crosstalk tests, or when adding channels externally for OOB timing tests or emulation of 3-level signals or signal de-emphasis. It provides the most complete jitter tolerance test for embedded and forward clocked devices.
Features and Specifications of the Agilent / Keysight N4903B J-BERT include:
- Data rates 150 Mb/s to 7 Gb/s or to 12.5 Gb/s pattern generator and error detector. Option to extended data rate to 14.2 Gb/s for pattern generator.
- >0.5 UI calibrated, compliant and integrated jitter injection: RJ, RJ-LF, RJ-HF, PJ1, PJ2, SJ, BUJ, ISI, sinusoidal interference, triangular and arbitrary SSC and residual SSC
- Arbitrary SSC profile and extended SSC range to characterize SATA/SAS and USB3 receivers under real-world condition
- Excellent signal performance and sensitivity
- Improved output signal performance
- Measures BER, BERT Scan, TJ with RJ/DJ separation, eye diagram, eye mask, BER contour, automated jitter tolerance, pattern capture, frame error rate (FER), or symbol error rate (SER) coded and retimed data streams
- Two adjustable data outputs with independent PRBS and pattern with 120 block pattern sequencer
- Variable output levels on trigger and aux data outputs
- All options are retrofittable and upgrade from N4903A possible
- Built-in clock data recovery with tunable and compliant loop bandwidth
- Supports testing of forwarded clock devices:
- Halfrate clock with variable duty cycle
- Jitter on clock and data
- Delay of jitter between clock and data
- PCIe 2.0 compliant jitter injection:
- LF-RJ and HF-RJ
- dual-tone PJ
- residual SSC
- electrical idle
- 16x FC testing with extended data rate for the pattern generator up to 14.2 Gb/s
- Wider PJ range up to 300 MHz
- Pattern generator key characteristics:
- Available as 7 and 12.5 Gb/s pattern generator without error detector (Options G07 and G13), extension to 14.2Gb/s (Option D14)
- Differential outputs with variable output levels for data, aux data, clock and trigger
- Lowest intrinsic jitter – 800 fs rms
- Transitions times < 20 ps
- Half-rate clock with variable duty cycle (Option 003)
- Pattern sequencer with up to 120 blocks and counted loops
- Second output channel (Option 002)
- Calibrated and integrated jitter injection with SJ, two-tone PJ, RJ/sRJ, BUJ, ISI, S.I. (Option J10, J20)
- SSC and residual SSC (Option J11)
- Automated jitter tolerance characterization sweep makes use of SJ and PJ using 610 ps or 220 ps delay line
- High precision delay control input to inject jitter from an external source
- Electrical idle state on data outputs
- Error detector key characteristics:
- True differential inputs to match today’s ports
- Built-in CDR with tunable loop-bandwidth up to 12 MHz
- Auto-alignment of sampling point
- Bit recovery mode for unknown data traffic (Option AO1)
- SER/FER analysis of coded and retimed data (Option A02)
- Burst mode for testing recirculating loop
- BER result and measurement suite
- Quick eye diagram and mask with BER contours
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